A complementary-metal-oxide-semiconductor (CMOS) solid state imaging apparatuses represents an image sensor in which a signal accumulated in a photodiode forming part of each of pixels is read out by an amplifier circuit including a MOS transistor. Such a CMOS solid state imaging apparatus can operate at low voltages, consume less power, and be integrated in one chip together with a peripheral circuit.
In view of the above, attention has been paid to CMOS solid state imaging apparatuses as image input devices used for compact cameras for personal computers and portable devices, such as cell phones. In recent years, an increase in the number of pixels have been demanded for CMOS solid state imaging apparatuses, and therefore the cell size per pixel tends to be reduced.
In a known solid state imaging apparatus, a thermal oxide film is generally formed, by local oxidation of silicon (LOCOS), in an isolation region for isolating a photodiode formed in a semiconductor substrate and semiconductor devices from one another. In the use of LOCOS, the width of the isolation region needs to be increased to provide a sufficient isolation property. Furthermore, when a thermal oxide film is formed by LOCOS, a bird's beak occurs and therefore the isolation region enters into an active region of the semiconductor substrate. This makes it necessary to previously secure a wide active region. In view of the above, the area of the isolation region occupied in each of pixels and the area of the active region occupied therein must be increased. This makes it difficult to reduce the size of the pixel.
The following known art is used as a measure for solving such a problem (see Patent Document 1). FIG. 14 illustrates a cross-sectional structure of a photodiode section of a solid state imaging apparatus according to a known example.
As illustrated in FIG. 14, a photodiode 62 including a P−-type silicon layer 55, an N-type silicon layer 54 and a P+-type silicon layer 56 is formed in the vicinity of the top surface of an N-type silicon substrate 53.
An isolation region 52 is formed in the vicinity of part of the top surface of the N-type silicon substrate 53 located around the photodiode 62 to extend from the uppermost surface of the N-type silicon substrate 53 to substantially the same depth as that of the N-type silicon layer 54 and have a shallow trench isolation (STI) structure in which a trench having inner walls covered with a silicon dioxide (SiO2) film 61 is filled with an insulating film made of SiO2 and any other material. Therefore, the photodiode 62 is electrically isolated from other peripheral devices in the top surface of the N-type silicon substrate 53.
Since in the known example the isolation region 52 is formed to have a STI structure, a bird's beak does not occur and therefore the isolation region 52 does not enter into a light-receiving area 51. Therefore, the area of the light-receiving area 51 is not reduced due to a bird's beak. As a result, a large light-receiving area 51 can be secured. Furthermore, in the case of the isolation region 52 of a STI structure, the width of an insulative material necessary for isolation is smaller than in the case of the isolation region 52 of a LOCOS structure or any other structure. This can reduce the area of the isolation region itself, resulting in the enhanced sensitivity of the photodiode.
Patent Document 1: Japanese Unexamined Patent Publication No. 2004-39832